In recent years, information processing apparatuses have significantly been improved in their performance. With this improvement, the data rates of data signals exchanged inside and outside the information processing apparatuses have also been increased.
When a reception circuit receives an input data signal, the reception circuit performs clock and data recovery (CDR) for recovering a value of the input data signal and a clock.
In one CDR method, an input data signal is sampled by using a clock (sampling clock) recovered from the input data signal, not by using a reference clock. In this method, the phase difference and the frequency difference between the sampling clock and the input data signal are detected to adjust the sampling clock. A 2× sampling method is used for detecting the phase of the sampling clock. In this method, sampling is performed twice per unit interval (UI). In addition, a 4× sampling method is used for detecting the frequency of the sampling clock. In this method, sampling is performed four times per UI.
In the above frequency detection method, a phase region from 0° to 360° is divided into four quadrants, and the quadrant in which an edge of an input data signal detected by using the sampling clock exists is detected. Next, a phase rotation direction is detected on the basis of the shift of the phases of edges over quadrants. On the basis of the phase rotation direction, whether the frequency of the sampling clock is lower or higher than that of the input data signal is detected, and a frequency adjustment value based on the detection result is outputted. See, for example, the following documents:    Japanese Laid-open Patent Publication No. 2005-252723;    Japanese Laid-open Patent Publication No. 2001-177397; and    U.S. Pat. No. 6,055,286.
However, with the above frequency detection method, when the frequency difference between the input data signal and the sampling clock is small, since the phase shift amount between edges of the input data signal is small, it takes time for the phases of the edges to shift over quadrants. Namely, the frequency detection takes time.
One solution to address this problem is outputting the same adjustment value until the next frequency difference is detected so that a larger shift amount is obtained per frequency difference detection. Namely, the gain used in frequency adjustment is equivalently increased. However, if a large shift amount is obtained per frequency difference detection, when the frequency difference between the input data signal and the sampling clock is small, an excessive adjustment could be made. As a result, the convergence could be deteriorated.
As described above, if a reception circuit using the conventional frequency detection method is used, it takes time for the frequency of the sampling clock to converge into a target frequency.